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We seek a highly talented researcher to explore novel compiler technologies and toolchains for next-generation computing architectures, including CPUs and AI accelerators, and analyze key software-hardware co-design trade-offs in coordination with cross-functional domain experts.

Tasks

  • Design and validate efficient compiler infrastructures and algorithms to maximize computational performance, optimize memory utilization, and generate highly efficient hardware-specific code.
  • Drive software-hardware co-optimization efforts, including kernel fusion, memory layout tuning, and operator scheduling for GPUs, TPUs, or custom accelerators.
  • Recognize and track technology trends across the compiler ecosystem, from traditional frameworks (LLVM, GCC) to modern AI stacks (MLIR, TVM, Triton), and propose novel technologies to improve compilation speed, execution performance, code size, and programmability.
  • Participate in strategic and business planning discussions.
  • Engage with local academic and industrial partners based on business requirements.
  • Independently lead the development and operation of research collaboration projects.

Requirements

  • MSc or PhD in Computer Science, Software Engineering, or a related field.
  • At least 1 year of relevant experience in compiler development, system software, or computer architecture.
  • Demonstrated expertise in compiler construction, covering front end parsing, middle end optimizations, and back end code generation.
  • Strong background and hands-on experience with foundational compiler infrastructures (e.g., LLVM, GCC) and/or modern deep learning compilers (e.g., MLIR, Apache TVM, XLA) – highly preferred.
  • Solid compiler fundamentals backed by substantial experience, including deep understanding of traditional optimizations (auto vectorization, loop transformations, register allocation, instruction scheduling) as well as modern AI specific techniques (computational graph optimizations, operator fusion, polyhedral compilation).
  • Experience in code generation and performance tuning for specialized hardware (e.g., custom SoCs, GPUs, NPUs, DSPs, many core architectures).
  • Strong understanding of hardware-software interfaces and interactions. Background in microarchitecture (memory hierarchies, instruction pipelines, SIMD/VLIW, on chip interconnects) is highly valued.
  • Experience in software-hardware co-optimization, MFU optimization, and AI solver optimization is strongly preferred.
  • Proficiency in C/C++ (and ideally Python), with a track record of writing clean, maintainable, and highly optimized code for complex systems.
  • Fluency in English (written and verbal), with excellent writing skills for clear and concise reporting.

Benefits

  • Collaborate with world-class scientists and engineers in an open, curiosity-driven environment.
  • Access to state-of-the-art technology and tools.
  • Opportunities for professional growth and development.
  • Competitive salary, and a high quality of life in Zurich, at the center of Europe.
  • Be part of innovative projects that make a difference.
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Über uns
Huawei Technologies Switzerland AG ist die Schweizer Gesellschaft des internationalen Technologieunternehmens Huawei. Das Unternehmen bietet ICT- und Telekommunikationslösungen für Netzbetreiber, Unternehmen und weitere Organisationen an und ist in der Schweiz unter anderem in den Bereichen Carrier-Netzwerke, Enterprise-Lösungen, Forschung, Consumer-Technologie und digitale Infrastruktur tätig. Huawei Schweiz arbeitet mit grossen Schweizer Telekommunikationsanbietern zusammen und betreibt neben dem Hauptsitz in Liebefeld weitere Standorte in Dübendorf, Zürich und Lausanne.
Das Team

We are a unique team of innovative, diverse individuals from multiple backgrounds, creating advanced Software and Compiler Architectures for general-purpose and AI computing systems. Our primary mission is driving new fundamental research and innovation to achieve breakthroughs in future computing systems.

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